Advances in error-correcting codes, such as convolution codes and trellis codes, have enabled designers of digital communications systems to achieve increased bit rates for a given level of error rate performance. One of the most significant developments in the area of digital error correcting codes are the recursive convolution codes collectively known as “turbo codes.” Turbo codes operate by combining a plurality of encoders with permuters to iteratively encode data to improve performance using a corresponding number of soft input/soft output decoders which operate iteratively.
An early description of turbo codes appears in C. Berrou, et. al, “Near Shannon limit error-correcting coding and decoding: Turbo codes,” Proc. 1993 Int. Conf. Communication (Geneva, Switzerland, May 1993), pp. 1064–1070. Berrou, et. al discloses a parallel-concatenated turbo code. The input data is applied to a first convolutional encoder and an interleaved version of the input data is applied to a second convolutional encoder. Some of the redundant bits generated by the encoders may be subjected to a puncturing prior to the mapping step in order to improve bandwidth efficiency.
While turbo codes can reduce the level of received signal-to-noise ratio to achieve a desired level of error rate performance, the complexity of turbo codes can create significant end-to-end delay, or latency, which is undesirable in many applications. In addition, parallel concatenated turbo codes, like the one described in Berrou, exhibit an error floor phenomenon wherein the improvement in coding gain is far less dramatic at lower error rates and may be comparable to, or even worse than, the lower error rates achieved using more conventional encoding and decoding.
Serial concatenated turbo codes have also been suggested as disclosed by S. Benedetto, et al, in “Serial concatenation of interleaved codes: Performance analysis, design, and iterative decoding,” IEEE Trans. Inform. Theory, vol. 44, pp. 909–926, May 1998. In a serially concatenated turbo code, the input data is applied to a first convolutional encoder and the output bits of the first encoder, after interleaving, are used as the input bits for a second convolutional encoder. The error floor phenomenon associated with parallel-concatenated turbo codes is less pronounced for serial-concatenated turbo codes, thereby providing better coding gain at lower error rates. However, the performance of these codes in the low signal-to-noise regions is generally not as good as turbo codes. Furthermore, these serial-concatenated turbo codes generally generate more redundant bits than in the parallel case, so that they are less bandwidth-efficient. Moreover, they too require prohibitive complexity with associated delays.
Neither the parallel-concatenated nor the serial-concatenated turbo codes described above are bandwidth efficient; each of the designs has a bandwidth efficiency of less than two bits per two-dimensional signal point when used with quadrature phase-shift-key (QPSK) modulation. More bandwidth-efficient parallel concatenated turbo codes have been designed, including, for example, “Bandwidth efficient parallel concatenated coding schemes,” by S. Benedetto, et al, Electron. Lett., vol. 31, pp. 2067–2069, 1995, and P. Robertson, et al, and “Coded modulation scheme employing turbo codes,” Electron. Lett., vol. 31, pp. 1546–1547, 1995. The arrangements described in these references achieve high coding gains at high error rate while featuring an improved bandwidth efficiency of a full 2 bits per 2D signal point by using rate-2/3 trellis codes designed jointly with a 2D 8-PSK signaling constellation in contrast to the convolutional codes with the 2D 4-PSK constellation used in the Berrou design. However, the Benedetto codes still exhibit the undesirable error floor phenomenon and associated long delays.
Moreover, the error floor tends to occur at high error probabilities when the turbo code is based on very simple constituent codes and when the block length is short (generally from several hundred to several thousand bits). For wireless communication systems, short block lengths and simple constituent codes are usually required. One motivation for these requirements is to keep the decoder simple enough to implement the decoding in a cost-effective manner. The complexity of the decoder has currently limited the application of turbo codes to the reverse link, so that the turbo decoder is implemented in hardware at the base station. In addition, turbo codes can be used in hybrid automatic repeat request (ARQ) schemes that use code combining, but these methods have not been implemented in any of the current telecommunication standards. One probable reason for this is that previously proposed code-combining ARQ techniques all require additional iterative maximum a posteriori (MAP) decoding of the entire packet when additional code symbols are received. This additional iterative decoding results in significantly higher processing requirements and longer delays. Thus, it desirable to consider other code structures that can provide similar or better performance than turbo codes while also reducing the complexity.
To overcome the inherent limitations of turbo codes, several authors have suggested the use of an outer code error correction code with a turbo inner code. J. D. Andersen suggested the use of an outer Bose-Chaudhuri-Hochquenghem (BCH) cyclic, error-correcting, code in the Proceedings of the 1995 IEEE International Symposium on Information Theory and the October Issue ofIEE Electronics Letters. Narayanan and Stuber suggested a variation on this scheme in the September 1997 issue of IEEE Communications Letters. Kim and Lee considered a variation of the BCH outer code in the Proceedings of the 2000 IEEE International Symposium on Information Theory, as did Takeshita et al in the April 2001 IEEE Transactions on Communications. A Reed-Solomon (a type of non-binary BCH) code was used an outer code with a turbo inner code by Costello et al in the Proceedings of the 1996 IEEE International Symposium on Information Theory and Its Applications and by Valenti in the Proceedings of the 2000 IEEE Military Communications Conference. 
In addition, single parity-check codes and concatenations of single parity-check codes have been investigated by many authors, including Caire et al in the Proceedings of the 1994 Global Telecommunications Conference, Hagenauer et al in the March 1996 IEEE Transactions on Communications, Ping et al in the September 1997 IEE Electronics Letter and the Proceedings of the 1998 IEEE International Conference on Communications, and Rankin and Gulliver in the August 2001 IEEE Transactions on Communications. 
However, while mitigating the inherent problems of using a turbo code alone, the above proposed paired inner and outer error correcting codes suffer from a significant reduction in code rates and fail to utilize the soft-outputs of the turbo decoder. Therefore, there is a need in the art to provide a new error-correcting code comprising an outer code error correction code with a turbo inner code that can significantly outperform existing coding schemes without requiring a significant reduction in code rate.
The following patents, describing various error coding schemes, are incorporated herein by reference to the extent they are not inconsistent with the disclosure, teachings, and principles of the subject invention: U.S. Pat. Nos. 4,785,451; 5,406,570; 5,446,747; 5,563,897; 5,729,560; 5,920,578; 5,996,104; 6,023,783; 6,028,897; 6,122,763; and 6,351,832.
All patents, patent applications, provisional applications, and publications referred to or cited herein, or from which a claim for benefit of priority has been made, are incorporated herein by reference in their entirety to the extent they are not inconsistent with the explicit teachings of this specification.